document number: 91374 www.vishay.com s09-1257-rev. b, 13-jul-09 1 power mosfet sihp18n50c, SIHF18N50C vishay siliconix features ? low figure-of-merit r on x q g ? 100 % avalanche tested ? high peak current capability ? dv/dt ruggedness ? improved t rr /q rr ? improved gate charge ? high power dissipations capability ? compliant to rohs directive 2002/95/ec notes a. drain current limited by maximum junction temperature. b. repetitive rating; pulse width limi ted by maximum junction temperature. c. v dd = 50 v, starting t j = 25 c, l = 2.5 mh, r g = 25 , i as = 17 a. d. i sd 18 a, di/dt 380 a/s, v dd v ds , t j 150 c. e. 1.6 mm from case. product summary v ds (v) at t j max. 560 r ds(on) ( )v gs = 10 v 0.225 q g (max.) (nc) 76 q gs (nc) 21 q gd (nc) 29 configuration single n - c hannel m os fet g d s to-220 g d s s d g to-220 fullpak ordering information package to-220 to-220 fullpak lead (pb)-free sihp18n50c-e3 SIHF18N50C-e3 absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 500 v gate-source voltage v gs 30 continuous drain current (t j = 150 c) a v gs at 10 v t c = 25 c i d 18 a t c = 100 c 11 pulsed drain current b i dm 72 linear derating factor to-220 1.8 w/c fullpak 0.3 single pulse avalanche energy c e as 361 mj maximum power dissipation to-220 p d 223 w fullpak 38 peak diode recovery dv/dt d dv/dt 5 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (peak temperature) d for 10 s 300 * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91374 2 s09-1257-rev. b, 13-jul-09 sihp18n50c, SIHF18N50C vishay siliconix note a. repetitive rating; pulse width limi ted by maximum junction temperature. the information shown here is a preliminary product proposal, not a commercial product datasheet. vishay siliconix is not commi tted to produce this or any similar product. this information should not be used for design purposes, nor construed as an of fer to furnish or sell such products. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient to-220 r thja -62 c/w fullpak - 65 maximum junction-to-case (drain) to-220 r thjc -0.56 fullpak - 3.29 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 500 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma - 0.6 - v/c gate-source threshold voltage (n) v gs(th) v ds = v gs , i d = 250 a 3.0 - 5.0 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 500 v, v gs = 0 v - - 25 a v ds = 400 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 10 a - 0.225 0.270 forward transconductance a g fs v ds = 50 v, i d = 10 a - 6.4 - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz - 2451 2942 pf output capacitance c oss - 300 360 reverse transfer capacitance c rss -2632 internal gate resistance r g f = 1.0 mhz, open drain - 1.1 - total gate charge q g v gs = 10 v i d = 18 a, v ds = 400 v -6576 nc gate-source charge q gs -21- gate-drain charge q gd -29- turn-on delay time t d(on) v dd = 250 v, i d = 18 a r g = 7.5 , v gs = 10 v -80- ns rise time t r -27- turn-off delay time t d(off) -32- fall time t f -44- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --18 a pulsed diode forward current i sm --72 body diode voltage v sd t j = 25 c, i s = 18 a, v gs = 0 v - - 1.5 v body diode reverse recovery time t rr t j = 25 c, i f = i s , di/dt = 100 a/s, v r = 35 v - 503 - ns body diode reverse recovery charge q rr -6.7-c reverse recovery current i rrm -30-a s d g
document number: 91374 www.vishay.com s09-1257-rev. b, 13-jul-09 3 sihp18n50c, SIHF18N50C vishay siliconix typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics, t c = 150 c (to-220) fig. 2 - typical output characteristics, t c = 150 c (to-220) fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature v ds , drain-to-so u rce v oltage ( v ) i d , drain c u rrent (a) 0 10 20 30 40 50 60 70 0612 1 8 24 30 7.0 v bottom to p v gs 15 v 14 v 13 v 12 v 11 v 10 v 9.0 v 8 .0 v 7.0 v 6.0 v 5.0 v t j = 25 c 0 10 20 30 40 0 6 12 1 8 24 30 7.0 v v ds , drain-to-so u rce v oltage ( v ) i d , drain c u rrent (a) bottom to p v gs 15 v 14 v 13 v 12 v 11 v 10 v 9.0 v 8 .0 v 7.0 v 6.0 v 5.0 v t j = 150 c i d , drain c u rrent (a) v gs , gate-to-so u rce v oltage ( v ) 0.01 0.1 1 10 100 567 8 910 t j = 150 c t j = 25 c t j , j u nction temperat u re ( c) r ds(on) , drain-to-so u rce on resistance ( n ormalized) 0 0.5 1 1.5 2 2.5 3 - 60 - 40 - 20 0 20 40 60 8 0 100 120 140 160 i d = 17 a v gs = 10 v
www.vishay.com document number: 91374 4 s09-1257-rev. b, 13-jul-09 sihp18n50c, SIHF18N50C vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area fig. 9 - maximum drain current vs. case temperature (to-220) capacitance (pf) v ds , drain-to-so u rce v oltage ( v ) 10 10 2 10 3 10 4 10 5 1101001000 v gs = 0 v , f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c iss c rss c oss q g , total gate charge (nc) v gs , gate-to-so u rce v oltage ( v ) 0 4 8 12 16 20 0306090120 i d = 17 a v ds = 250 v v ds = 100 v v ds = 400 v v sd , so u rce-to-drain v oltage ( v ) i sd , re v erse drain c u rrent (a) 0.1 1 10 100 0.2 0.5 0. 8 1.1 1.4 t j = 150 c t j = 25 c v gs = 0 v v ds , drain-to-so u rce v oltage ( v ) i d , drain c u rrent (a) t c = 25 c t j = 150 c single p u lse operation in this area limited b y r ds(on) 1 ms 10 ms 100 s 10 3 1 10 10 2 10 10 2 10 3 10 4 0.1 i d , drain c u rrent (a) t c , case temperat u re (c) 0 5 10 15 20 25 50 75 100 125 150
document number: 91374 www.vishay.com s09-1257-rev. b, 13-jul-09 5 sihp18n50c, SIHF18N50C vishay siliconix fig. 10 - normalized thermal transient impedance, junction-to-case (to-220) fig. 11 - normalized thermal transient impedance, junction-to-case (to-220fp) fig. 12a - switching time test circuit fig. 12b - switching time waveforms 10 -4 10 -3 10 -2 0.1 1 n ormalized effecti v e transient thermal impedance 0.01 0.1 1 p u lse time (s) single p u lse 0.02 0.05 0.1 0.2 d u ty cycle = 0.5 10 -4 10 -3 10 -2 0.1 10 n ormalized effecti v e transient thermal impedance 0.01 0.1 1 p u lse time (s) single p u lse 0.02 0.05 0.1 0.2 d u ty cycle = 0.5 1 p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f
www.vishay.com document number: 91374 6 s09-1257-rev. b, 13-jul-09 sihp18n50c, SIHF18N50C vishay siliconix fig. 13a - unclamped inductive test circuit fig. 13b - unclamped inductive waveforms fig. 14a - basic gate charge waveform fig. 14b - gate charge test circuit r g i as 0.01 t p d.u.t l v ds + - v dd 10 v v ary t p to o b tain req u ired i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + -
document number: 91374 www.vishay.com s09-1257-rev. b, 13-jul-09 7 sihp18n50c, SIHF18N50C vishay siliconix fig. 15 - for n-channel vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91374 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs = 10 v* v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor current d = p. w . period + - + + + - - - * v gs = 5 v for logic level and 3 v drive d evices peak diode recovery dv/dt test circuit r g v dd ? dv/dt controlled by r g ? i sd controlled by duty factor "d" ? d.u.t. - device under test d.u.t circuit layout considerations ? low stray inductance ? ground plane ? low leakage inductance current transformer
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